The present invention relates to a semiconductor evaluation apparatus for evaluating chargeup damage of an actual device in the semiconductor device fabrication process.
Following the requirement of fineness in the semiconductor device fabrication process, ion implantation technique, plasma dry etching technique, and the like have been introduced in semiconductor device fabrication apparatuses and a semiconductor substrate is to be exposed frequently to an electron, ions, plasma, and the like and thus how to suppress a chargeup damage has come up as a matter in the fabrication process.
Further, requirements for fineness of elements and variety of devices are further acceleratedly increased following the system large scale integration (LSI) and the effect of the chargeup damage has become a more sensible matter for an element. Nevertheless, its mechanism and the measurement method have not yet sufficiently established and most part of the matter has been left unclear today.
Conventional evaluation methods of the chargeup damage are mainly a breakdown voltage measurement method for an ultra thin oxide film and a method using an antenna MOS transistor, an EPROM, an EEPROM and the like.
The former is a method for checking whether a gate oxide film is broken or not by using an ultra thin oxide film or checking breakdown property (TDDB: Time dependent Dielective Breakdown) with the lapse of time by forcibly applying stress by charging with electric charge.
This method is to measure the deterioration of the oxide film caused when the charged up and accumulated electric charge penetrates the gate oxide film with an ultra thin film thickness through and reaches a substrate. Problems are that the ultra thin oxide film used is not used in the relevant fabrication process and that dielectric breakdown is natural to take place if the evaluation is carried out using a thinner film to make judgment difficult.
A substrate already bearing an oxide film and produced in the outside is mounted in some cases and inserted directly in an apparatus in other cases and thus the evaluation sometimes considerably deviates from the fabrication process and the device structure. Further, since the measurement is carried out in a distraction mode, the method is insufficient in the sensitivity to detect the property alteration which does not result in the distraction mode of an actual device.
Actually, evaluation is impossible in many cases in the fabrication process of an actual device of such as a bipolar IC and an analog element of CCD. Also, the method has disadvantages that a large pattern surface area is required, it takes a long time to evaluate, and that a large number of samples are required for getting statistic data.
In the method using an antenna MOS transistor, there are many cases of using an ultra thin oxide film for the gate oxide film and in such cases, the same problems as described above are brought forth. Since evaluation is carried out in a MOS transistor, evaluation of the transistor properties and the hot carrier life properties is also made possible other than the evaluation of the withstand voltage property of the gate oxide film and the TDDB property.
Further, since the gate is composed as to have an antenna structure, actual pattern addition is possible and also evaluation of actual dry etching and resist removal in the fabrication process is made possible.
However, an electrode for measurement has to be installed in an antenna gate for evaluation measurement and for that, the charge accumulated in a floating gate is possibly discharged at the time of the process of forming a layer for the electrode.
Hence, the method probably misses the phenomenon that the gate is broken and deteriorated by the electric charge since the electric charge together with remaining charge is expelled to the antenna in the process, for example, in the film formation process by plasma oxide, after the process of layer formation for electrode.
In case of employing this method for evaluating the transistor properties by their alteration, the sensitivity is improved more than that by the withstand voltage evaluation, however in the case where the ultra thin oxide is used, it becomes difficult to make validity of the results in relation to an actual product and the actual fabrication process. Further, it also becomes difficult to grasp to which extent of the chargeup the property""s alteration value is related to and to judge the chargeup is positive or negative.
In the case of employing the EEPROM, EPROM or other memory device, in many cases, the chargeup phenomenon is evaluated based on the alteration of the memory properties by setting a produced product or device as it is in an apparatus. The problems in such cases are whether the product or device can be set as it is in the apparatus and that the treatment in the actual process cannot be carried out and the device structure is different from that in the actual fabrication process.
Hence, if the evaluation is possible, it is unclear what the evaluation results imply in the actual product and the actual fabrication process of the product. Nevertheless, the extent of the chargeup can be measured based on the output electric current value and Vth, which are properties of a memory, the method gives clearer evaluation results than the former methods as above described.
Also, although the imperfect judgment, the method makes it possible to grasp whether the chargeup is positive or negative within the operation range.
Regarding the problems in the present techniques, that the evaluation element cannot be produced in the relevant process is a main and big obstacle and due to that, evaluation is carried out by way of using the ultra thin oxide film and an element such as EEPROM, EPROM with the different structure.
If the process and the device structure are different, the resistance of the contact face with a capacity and an apparatus differs and thus it can easily be supposed that the chargeup state is also different from that in the actual process and the actual product. Even in the dry etching process, actually a material to be etched is etched and an underlayer material is over etched in the situation that a resist is patterned. It is desirable that the chargeup can be evaluated at that time.
Further, although the chargeup phenomenon is supposedly affected with the CVD process, metal film growth, thermal treatment, and the like before and after the etching process and also with the hydrogen content in the film, the well structure, the wiring structure, and the like, it has not sufficiently been made clear.
The state of the art is described above, mainproblems arethat the measurement sensitivity is low, the measurement evaluation takes a long time, evaluation is impossible for analog elements, the evaluation constitution is insufficient to evaluate the chargeup damage caused in the actual fabrication process, the evaluation is impossible to evaluate the chargeup damage relevant to the actual product on completion of the diffusion process, and that no correlation of the evaluation results with the properties of the actual product and actual devices is made clear.
Objects of the present invention is:
1. to improve the measurement sensitivity relevant to the chargeup damage;
2. to shorten the measurement evaluation time relevant to the chargeup damage;
3. to find the chargeup damage occurring process;
4. to make evaluation possible for digital and analog elements (MOS, a bipolar IC, the CCD process);
5. to equalize evaluation to that in the actual product by simulation of the actual process and the entire process; and
6. to make a relation of the chargeup damage with the properties of the actual product and the actual device.
The means for solving the above described objects 1 to 6 are as follows:
1. to employ a floating type antenna gate or diffusion layer and both N channel and P channel elements;
2. to employ a manner of employing the numerical evaluation by using an element for evaluation and for comparison but not depending on time dependency;
3. to employ a variety of shielding films and parallel formation of a variety of antennas corresponding to the occurrence process;
4. to employ digital and analog elements (MOS, a bipolar IC, and a CCD element);
5. to simulate the actual process for an evaluation element and the entire process of the fabrication process; and
6. to simultaneously mount the chargeup damage evaluation element with the actual product and the actual device.
Hereinafter, the effects of above described means will be described.
1. The effect of the floating type antenna gate or the diffusion layer
If the extent of the chargeup is intense, charge penetrates a substrate from a gate and causes breakdown of an oxide film and if the extent is low, the charge is left as it is, and therefore, evaluation is made possible even in the process thereafter by making a floating structure and consequently, to employ the floating type antenna gate has an effect of improving the measurement sensitivity.
If an electrode is attached to the gate, the charge escapes only by bringing a probe into contact with the gate at the time of measurement. Therefore, the measurement is carried out without bringing the probe into contact with the gate to carry out evaluation based only on the electric current flowing between a source and a drain of the antenna MOS transistor. If the positive charge is accumulated in the gate, an N-type transistor is turned on and electric current flows and a P-type transistor is turned off and no electric current flows. If the negative charge is accumulated in the gate, the P-type transistor is turned on and electric current flows. In such a manner, by making both N and P type transistors ready, the effect of judging whether the charge is positive or negative can be obtained. The same effects are given in case of the diffusion layer. A floating diffusion layer is made ready and an another impurity-type diffusion layer formed as to surround the region is made ready to measure the resistance by attaching electrodes to both ends. Depending on the quantity of the charge accumulated in the floating diffusion layer, electric potential affects the resistor below and it causes change of the depletion layer width and fluctuates the resistance values. The chargeup voltage can be calculated from the alteration of the resistance values. Further even in case of a simple diffusion resistor, the same effects are made available by using a high resistance resistor. The chargeup damage to invert the surface of the low concentration diffusion layer is made possible to be detected by the leakage between high concentration diffusion layers in the low concentration diffusion layer.
2. The effect of the comparison element
A practical gate voltage of the floating type antenna gate is made possible to be calculated by comparing the output electric current of a MOS transistor having the floating type antenna gate with the gate voltage and the output electric current property of a standard MOS transistor for comparison.
In the same manner, in case of the resistance of a diffusion layer having a floating diffusion layer there above, the practical voltage of the floating diffusion layer is made possible to be calculated from the voltage and the resistance property of the lower diffusion layer by making a floating diffusion layer equipped with an electrode ready as the comparison element. In any case, since the chargeup voltage including plus and minus characteristic of the floating part can be obtained as a numerical value even by measurement of only one element by comparison with the comparison element, the measurement time can be shortened. On the other hand, in case of measurement of the withstand voltage, the measurement takes a long time since the measurement depends on the judgment whether the dielectric breakdown takes place or not and since a stable numerical value cannot be obtained unless statistic numerical value measurement is carried out.
3. The effect of using a variety of antennas and shielding film
The chargeup generation process can be found by investigating in which antennas of the layer structure the chargeup takes place by making several types of antenna gates ready in case of a MOS transistor having the floating type antenna gate. Also, the generation process can be found by investigating which layers show the shielding effect by forming a variety of types of shielding films on the antenna gate. The shielding films can be added to a resistance element, a diffusion layer leakage measurement element, and a variety of device elements and thus have the function of fining the generation process.
4. The effect of employing the digital and analog element (MOS, bipolar IC, CCD process)
Shielding films and etching layers are additionally formed in a resistance element, a diffusion layer junction leak, an NPN bipolar element, a lateral PNP element, a vertical PNP bipolar element, a photodiode-attached perpendicular CCD element, and the like and an antenna layer is additionally formed in some of elements. The films and the layers have the function of finding the effect on the properties on a practical product.
5. The effect of evaluation element by simulating practical process and entire process of fabrication process
The chargeup phenomenon is sometimes not actualized unless the practical device structure is composed. For example, in case of a batch type dry etching apparatus in which substrates are to be set in a stage, the coupling capacity differs depending on the rear side state of the substrates, the oxide film remaining state, the specific resistance values of the substrates, existence of epitaxial layers, the well structure, the constitutions on the substrate upper faces, and the like. Practical fabrication process as to obtain the practical device structure is simulated.
6. The effect of simultaneous mounting of chargeup damage evaluation element with practical product and practical device
By simultaneously mounting the evaluation element with the practical product, the correlation of the property of the practical product and the chargeup damage can be found. It can clearly be judged whether gate oxide film break is caused by chargeup damage and whether the remaining chargeup voltage which is not so high as to cause gate oxide film break is positive or negative and also the correlations can be made clear among the alteration of the resistance values, the surface leakage current, a variety of the device properties and product yield ratios.
An evaluation method of an embodiment 1 of the present invention for semiconductor chargeup damage is characterized in that a semiconductor element having a wiring layer having an antenna effect is installed in the periphery of a practical device or product formed in a semiconductor substrate and necessary to be evaluated, the antenna gate of the foregoing semiconductor element is composed as to have an electrode-free floating structure, and evaluation is carried out based on the electric current flowing between the source and the drain of the MOS transistor of the foregoing semiconductor element without attaching a probe to the gate.
A semiconductor device of an embodiment 2 of the present invention comprises elements for evaluation comparison characterized in that the elements are a first semiconductor element comprising a wiring layer having an antenna effect and a second semiconductor element comprising a gate having no such a wiring layer having the antenna effect but equipped with an electrode and both elements are installed in the periphery of a practical device formed in a semiconductor substrate and necessary to be evaluated.
A semiconductor device of an embodiment 3 of the present invention as described in the embodiment 2 is composed of any one of a MOS transistor, a bipolar transistor, a CCD transmission element, a CCD light receiving element, a discrete element, and a resistance element comprising a diffusion layer and a wiring layer, these elements in combination, and elements arranged in parallel and selected from them.
A semiconductor device of an embodiment 4 of the present invention as described in the embodiment 2 comprises the first semiconductor element characterized in that a plurality of elements comprising the wiring layers having the antenna effect which the first semiconductor element is provided with are installed in the periphery of the practical device while the quality, the type, the size, the surface area, the length, the width, and the intervals of the wiring layers being changed.
A semiconductor device of an embodiment 5 of the present invention as described in the embodiment 2 comprises the first semiconductor element comprising the wiring layer having solely the antenna effect or the wiring layer having the antenna effect in combination with a wiring layer having the shielding effect or the wiring layer having the antenna effect in combination with a wiring layer for which the treatment process of the semiconductor fabrication process is added.
A semiconductor device of an embodiment 6 of the present invention is characterized in that elements having N type and P type impurity types of the diffusion layers or the wiring layers of a variety of the respective semiconductor elements having the structure described in the embodiment 2 are installed in the peripheral parts, respectively.
A semiconductor device of an embodiment 7 of the present invention, in the case where the first and the second semiconductor elements having the structure as described in the embodiment 2 are diffusion layer elements, is characterized by comprising an element in which impurity diffusion layers are disposed face to face at a constant separation distance as to measure and evaluate the leakage current between impurity layers with the same impurity type and at the same time characterized in that an element which has the same structure as that of the former and in which a wiring layer, an insulating layer, or a mask layer having the antenna or shielding effect or subjected to processing treatment or an element subjected to processing treatment is formed on the upper part of the diffusion layer is installed in the periphery.
A semiconductor device of an embodiment 8 of the present invention, in the case where the first and the second semiconductor elements having the structure as described in the embodiment 2 are diffusion resistance elements, is characterized by comprising a first diffusion resistance element in which a second diffusion layer is formed in a first diffusion layer and electrodes for resistance measurement are attached to the respective ends and characterized in that a second diffusion resistance element having a structure composed by eliminating the electrode structures attached to both ends of the second diffusion layer from the above described first diffusion resistance element all together with the contact hole formation process and leaving the electrode structures attached to both ends of the first diffusion layer resistance element as they are is installed in the periphery of the first diffusion resistance element.
A semiconductor device of an embodiment 9 of the present invention, in the case where the first and the second semiconductor elements having the structure as described in the embodiment 2 are MOS transistor elements, is characterized by comprising a first antenna MOS transistor element having an electrode for measurement attached to the gate having the antenna structure and characterized in that a second antenna MOS transistor element having a floating gate structure composed by eliminating the electrode for measurement attached to the gate having the antenna structure from the above described first antenna MOS transistor element all together with the contact hole formation process is installed in the periphery of the above described first antenna MOS transistor element.
A semiconductor device of an embodiment 10 of the present invention, in the case where the first and the second semiconductor elements having the structure as described in the embodiment 2 are antenna MOS transistor elements, is characterized by comprising a first looped antenna MOS transistor element having a looped antenna gate or antenna wiring layer connected to the transistor and characterized in that a second antenna MOS transistor element composed by cutting a part of the looped antenna gate or antenna wiring layer of the above described first looped antenna MOS transistor element and making the gate or wiring layer non-looped is installed in the periphery of the above described first antenna MOS transistor element.
A semiconductor device of an embodiment 11 of the present invention, in the case where the first and the second semiconductor elements having the structure as described in the embodiment 2 are antenna MOS transistor elements, is characterized by comprising a group of first antenna MOS transistor elements having several varied intervals between neighboring antenna gate or antenna wiring layers while keeping the width of the antenna gates or the antenna wiring layers connected to the gates of the respective transistors constant and characterized in that a group of second antenna MOS transistor elements having several varied widths of the antenna gates or the antenna wiring layers connected to the gates of the respective transistors while keeping the intervals between neighboring antenna gate or antenna wiring layers constant are installed in the periphery of the above described group of the first antenna MOS transistor element.
A semiconductor device of an embodiment 12 of the present invention as described in the embodiment 11 is characterized in that one of a plurality of antenna gates or antenna wiring layers composing pattern density and having specified widths and specified intervals is connected with each gate of the respective transistors of the above described antenna MOS transistor element group.
A semiconductor device of an embodiment 13 of the present invention, in the case where the first and the second semiconductor elements having the structure as described in the embodiment 2 are antenna MOS transistor elements, is characterized by having the structure in which gates of the above described transistors are connected to the drains of other select MOS transistors, the antenna diffusion layers with the same impurity type as that of the source and drain diffusion layers of the above described MOS transistors are connected as to be overlaid on the source diffusion layers of the above described select MOS transistors, and the charge accumulated in the above described antenna diffusion layers is led to the gates of the antenna MOS transistors by turning on the gates of the above described select MOS transistors.
A semiconductor device of an embodiment 14 of the present invention, in the case where the first and the second semiconductor elements having the structure as described in the embodiment 2 are antenna MOS transistor elements, is characterized by having the structure in which gates of the above described transistors are connected to the drains of other select MOS transistors, the antenna diffusion layers having a device structure with the same impurity type as that of the source and drain diffusion layers of the above described MOS transistors or an LSI structure or an independent element structure are connected as to be overlaid on the source diffusion layers of the above described select MOS transistors, and the charge accumulated in the above described antenna diffusion layers is led to the gates of the antenna MOS transistors by turning on the gates of the above described select MOS transistors.
A semiconductor device of an embodiment 15 of the present invention as described in the embodiment 14 is characterized by comprising a structure making the operation of the device structure comprising the antenna diffusion layers therein or the above described LSI structure or the above described independent element structure possible.
A semiconductor device of an embodiment 16 of the present invention, in the case where the first and the second semiconductor elements having the structure as described in the embodiment 2 are antenna MOS transistor elements, is characterized by having the structure in which gates of the above described transistors are connected to the drains of other select MOS transistors, the antenna diffusion layers having a device structure with the same impurity type as that of the source and drain diffusion layers of the above described MOS transistors or an LSI structure or an independent element structure are connected as to be overlaid on the source diffusion layers of the above described select MOS transistors, and the charge accumulated in the above described antenna diffusion layers is led to the gates of the antenna MOS transistors by turning on the gates of the above described select MOS transistors and is characterized by having the structure in which drains of other reset MOS transistors are additionally connected to the gates of the above described antenna MOS transistor elements, sources of the above described reset MOS transistors are earthed to a substrate or an electric power source, and the charge accumulated in the gates of the above described antenna MOS transistor elements is released to the substrate or the electric power source side by turning on the gates of the above described reset MOS transistors.
A semiconductor device of an embodiment 17 of the present invention is characterized by additionally comprising a yield ratio evaluation element capable of evaluating disconnection, bridge short circuiting, interlayer leakage, wiring resistance, contact resistance, junction leakage, transistor properties or element properties relevant to the yield ratio of the diffusion layers, the wiring layers, the connection holes, transistors and a variety of elements in the respective steps of the semiconductor fabrication process or a yield ratio evaluation element comprising an address decoder circuit for detecting defective sites, other than a variety of the semiconductor elements actualized according to the embodiment 2.